In the manufacture of silicon semiconductor integrated circuits, interlevel dielectrics may be formed by a multi-step technique. The first step involves the deposition (usually in a plasma) of a relatively conformal dielectric layer which covers runners and generally fills the spaces between the runners. The dielectric is then etched back anisotropically to form spacers (although some dielectric may be permitted to remain on top of the runners and the substrate supporting the runners). Then a second dielectric deposition is performed (also usually in a plasma) and the second dielectric is subjected to a planarizing etch-back. The double-deposition procedure helps to prevent the formation of soft oxides or voids in the dielectric between the runners.
After the interlevel dielectric is completely formed, vias may be opened in the dielectric to expose portions of the underlying conductors so that an upper level of metalization may be connected through the vias. It is believed that subsequent to via opening, either chemical attack or water adsorption tends to occur within the via at the interface between the dielectric layers created by the above-described dual deposition process. Subsequent metal deposition within the via is degraded, thus adversely affecting integrated circuit performance.